This invention relates generally to computer systems and more particularly to devices used to drive signals onto and receive signals from a computer bus.
As it is known in the art, computer systems generally include a device referred to as a central processor unit which is used to execute computer instructions to perform some function. The central processing unit generally referred to as a CPU communicates with other devices in the computer system via a communications network generally referred to as a computer bus or system bus. Other devices commonly coupled to the system bus include memory systems such as main memory and more persistent type of storage systems such as magnetic disk type storage systems. These devices including the CPU are generally not connected directly to the system bus but rather are coupled to the bus through a device called a bus interface.
The bus interface device for a CPU may be quite different than that for a main memory or for a magnetic disk device. Moreover, for persistent storage such as magnetic disk, an interface module called a I/O bus adapter is often used to interface the system bus to an I/O bus (input/output bus) to which are connected several disk storage devices.
In general however, all of these interfaces on a particular bus use a common set of devices called bus drivers and bus receivers to send and receive logic signals with proper voltage levels and appropriate drive capacity to insure reliable transfers of data on the bus.
As it is also known, system buses generally carry information including address information, control information, and data. Busses transfer this information in a logical manner as determined by the design of the system. This logical manner is referred to as the bus protocol.
One problem that is common with system buses is that is as CPUs process information faster, it is necessary to provide a concomitant increase in bus transfer rate to permit more address, control, and data to be transferred at faster rates on the bus so as not to obviate the advantages obtained by use of a faster CPU.
As is also known in the art, each of the BUS interface circuits include the aforementioned BUS driver and BUS receiver. In a typical computer system, a plurality of conductors are used to provide the BUS between a plurality of interconnected devices. Each of the lines typically has a BUS driver and a BUS receiver associated with each one of the devices connected to it. Thus, in a typical computer system, one BUS driver may be required to drive as many as three or more receivers coupled to the corresponding line. Some buses have special lines which also permit multiple drivers to drive a line.
One problem with conventional drivers is particularly related to those bus lines which are designed to have multiple drivers drive the BUS lines concurrently (i.e., a line in which multiple drivers can provide signals to drive the line during a particular cycle). Examples of such lines include an arbitration line or a busy line for example. The problem associated with multiple drivers driving a signal line is that as such multiple drivers drive their signals on the line the drivers can produce transients voltages which are sufficiently high to cause parasitic currents to flow through natural diodes formed in the bulk or substrate material supporting the circuits. If not adequately compensated for such currents can cause latch-up or under severe conditions such transients having sufficiently high magnitude can destroy the circuit.
A further problem particularly with high speed buses is that the conductors of the bus present an inherent inductance which provides a back EMF when current changes direction. This back EMF can also cause an overshoot transient which can disrupt the device or damage the device.
In the past to overcome these overshoot problems, therefore, it was necessary to provide a design and process to ensure that overshoot would not be effective in causing damage to the devices or latching up conditions in the chip.
Alternative arrangements have been to provide diodes coupled between the signal lines and power lines to clamp the lines between tolerable voltage limits. These approaches have drawbacks. In particular, the diode approach typically presents a large parasitic capacitance to the bus conductor which causes a delay in the recovery of the diode and hence a reduction in bus speed. Whereas, the former approach relies upon good characterization of the semiconductor process used to provide the devices, the characterization may not always accommodate variations due to aging, processing and temperature changes.